The present invention relates generally to content addressable memory (CAM) devices.
A content addressable memory (CAM) device is a storage device that can be instructed to compare a specific pattern of comparand data with data stored in its associative CAM array. The entire CAM array, or segments thereof, are searched in parallel for a match with the comparand data. If a match exists, the CAM device indicates the match by asserting a match flag. Multiple matches may also be indicated by asserting a multiple match flag. The CAM device typically includes a priority encoder to translate the matched location into a match address or CAM index and outputs this address to a status register.
Each CAM cell conventionally includes a comparator and a random access memory (RAM) element. The CAM array may be partitioned into separate segments in which one segment stores CAM or compare data to be compared with the comparand data, and another segment stores associated RAM data corresponding to each of the CAM or compare locations. Once a match between the CAM data and the comparand data is determined, the associated RAM data for the matched location may be output to a status register. The RAM data and/or the CAM data may then be read from the status register.
Conventional CAM devices require more than one clock cycle to perform a write and compare instruction. For example, a typical write and compare instruction requires at least three clock cycles: a first clock cycle to present a compare instruction and/or comparand data to the CAM device, perform the search, and generate a match flag and multiple match flag signal; a second clock cycle to instruct the CAM device to output the matching CAM address or index; and, a third clock cycle to instruct the CAM device to output the associated data and status information (e.g., skip bit, empty bit, full flag, as well as, match and multiple match flags) for the matched location. With conventional cycle times generally running at 100 nanoseconds (ns), it requires at least 300 ns to complete this process. This generally limits the search rate of conventional CAM devices to approximately 1 to 3 million searches per second. This also generally limits the number of ports, segments, or devices that can be supported by a conventional CAM device in a switch or router environment.
The multi-clock cycle process has generally been required due to the architecture of conventional CAM devices. Most CAM devices include a general purpose bi-directional bus that keeps the pin count of the CAM devices to a minimum (e.g., 44 pins). The bi-directional bus is used to load comparand data and instructions into the CAM device. The bi-directional bus is also used to output the matched address, associated data, and status bits from a status register in the CAM device. Because this bus is shared with so many input and output functions, it requires many clock cycles to multiplex data on the bus.
CAM devices that have separated the general purpose bi-directional bus into a data input bus and a data output bus, still require at least three clock cycles to perform the write and compare operation described above, namely: one clock cycle to load the write and compare instruction and/or load the comparand data and perform the comparison with CAM array; one clock cycle to access the associated data; and, one clock cycle to instruct the CAM device to output the match address, associated data, and/or status information.
As applications for CAM devices increase in speed, there has been a desire for faster CAM devices that have shorter search times, or preferably, can execute a write and compare instruction in a fewer number of clock cycles. For example, it is desirable to have a CAM device that can be used as an address filter or address translator in an ethernet switch or router that operates at data rates of 100 Megabits per second (Mb/s) to 1 Gigabits per second (Gb/s). It is also desirable to have a CAM device that can be used to implement fast routing tables in Internet Protocol (IP) switches. As the number of ports, segments, or devices that are supported by the switches or routers increases, the time required for the supporting CAM device to perform a write and compare operation (e.g., address filter or translation operation) decreases. For example, to support a 1 Gb/s ethernet switch, a CAM device supporting approximately three ports should advantageously be able to perform a single write and compare instruction in approximately 100 ns or faster. A CAM device supporting approximately six ports should advantageously be able to perform a single write and compare instruction in approximately 50 ns or faster.
A content addressable memory (CAM) device is disclosed. The CAM device is a synchronous device that may perform all of the following operations in one clock cycle: (1) receive comparand data from a comparand bus; (2) receive an instruction from an instruction bus instructing the CAM device to compare the comparand data with a first group of CAM cells in a CAM array; (3) perform the comparison of the comparand data with the first group of CAM cells; (4) generate a match address for a location in the CAM array that stores data matching the comparand data; (5) access data stored in a second group of CAM cells in the CAM array, wherein the second group of CAM cells may store data associated with the matched location; and (6) output to an output bus the match address, the data stored in the second group of CAM cells, and/or status information corresponding to the matched address or the second group of CAM cells. The status information may include a match flag, multiple match flag, full flag, skip bit, empty bit, or a device identification for the CAM device. The CAM array may also include ternary CAM cells that are individually maskable so as to effectively store either a logic one, logic zero, or a don""t care state for compare operations.
Other objects, features, and advantages of the present invention will be apparent from the accompanying drawings and from the detailed description which follows below.